Testing cannot cover all execution schedules in concurrent software. Model checking, however, is capable of verifying the outcome of all possible executions. It has been applied s...
The paper proposes an efficient terminal and model order reduction method for compact modeling of interconnect circuits with many terminals. The new method is inspired by the rece...
Pu Liu, Sheldon X.-D. Tan, Boyuan Yan, Bruce McGau...
As interconnect feature sizes continue to scale to smaller dimensions, long interconnect can dominate the IC timing performance, but the interconnect parameter variations make it ...
Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas
This paper proposes a novel wideband modeling technique for high-performance RF passives and linear(ized) analog circuits. The new method is based on a recently proposed sdomain h...
Large and sparse rational eigenproblems where the rational term is of low rank k arise in vibrations of fluid–solid structures and of plates with elastically attached loads. Exp...