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IEEEPACT
2000
IEEE
15 years 7 months ago
Instruction Scheduling for Clustered VLIW DSPs
Recent digital signal processors (DSPs) show a homogeneous VLIW-like data path architecture, which allows C compilers to generate efficient code. However, still some special rest...
Rainer Leupers
ITC
2000
IEEE
124views Hardware» more  ITC 2000»
15 years 7 months ago
Wrapper design for embedded core test
A wrapper is a thin shell around the core, that provides the switching between functional, and core-internal and core-external test modes. Together with a test access mechanism (T...
Yervant Zorian, Erik Jan Marinissen, Maurice Lousb...
133
Voted
FPL
1999
Springer
147views Hardware» more  FPL 1999»
15 years 7 months ago
Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs
This paper details the development, implementation, and results of Synthia, a system for the synthesis of Finite State Machines (FSMs) to field-programmable logic. Our approach us...
George A. Constantinides, Peter Y. K. Cheung, Wayn...
IPPS
1998
IEEE
15 years 7 months ago
Utilization and Predictability in Scheduling the IBM SP2 with Backfilling
Scheduling jobs on the IBM SP2 system is usually done by giving each job a partition of the machine for its exclusive use. Allocating such partitions in the order that the jobs ar...
Dror G. Feitelson, Ahuva Mu'alem Weil
122
Voted
AAAI
2010
15 years 4 months ago
Bypassing Combinatorial Protections: Polynomial-Time Algorithms for Single-Peaked Electorates
For many election systems, bribery (and related) attacks have been shown NP-hard using constructions on combinatorially rich structures such as partitions and covers. It is import...
Felix Brandt, Markus Brill, Edith Hemaspaandra, La...