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» Output-Determinacy and Asynchronous Circuit Synthesis
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ENTCS
2008
110views more  ENTCS 2008»
13 years 7 months ago
Performance Evaluation of Elastic GALS Interfaces and Network Fabric
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficient...
JunBok You, Yang Xu, Hosuk Han, Kenneth S. Stevens
APN
2005
Springer
14 years 1 months ago
Determinate STG Decomposition of Marked Graphs
STGs give a formalism for the description of asynchronous circuits based on Petri nets. To overcome the state explosion problem one may encounter during circuit synthesis, a nondet...
Mark Schäfer, Walter Vogler, Petr Jancar
ICCAD
2008
IEEE
133views Hardware» more  ICCAD 2008»
14 years 4 months ago
Module locking in biochemical synthesis
—We are developing a framework for computation with biochemical reactions with a focus on synthesizing specific logical functionality, a task analogous to technology-independent...
Brian Fett, Marc D. Riedel
LCTRTS
2010
Springer
13 years 5 months ago
Translating concurrent action oriented specifications to synchronous guarded actions
Concurrent Action-Oriented Specifications (CAOS) model the behavior of a synchronous hardware circuit as asynchronous guarded at an abstraction level higher than the Register Tran...
Jens Brandt, Klaus Schneider, Sandeep K. Shukla