Sciweavers

5668 search results - page 1062 / 1134
» Overlaps in Requirements Engineering
Sort
View
CODES
2007
IEEE
14 years 5 months ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling
CODES
2007
IEEE
14 years 5 months ago
HW/SW co-design for Esterel processing
We present a co-synthesis approach that accelerates reactive software processing by moving the calculation of complex expressions into external combinational hardware. The startin...
Sascha Gädtke, Claus Traulsen, Reinhard von H...
CODES
2007
IEEE
14 years 5 months ago
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
Networks on Chip (NoC) have emerged as the design paradigm for scalable System on Chip communication infrastructure. A growing number of applications, often with firm (FRT) or so...
Andreas Hansson, Martijn Coenen, Kees Goossens
COMSWARE
2007
IEEE
14 years 5 months ago
On Optimal Performance in Mobile Ad hoc Networks
In this paper we are concerned with finding the maximum throughput that a mobile ad hoc network can support. Even when nodes are stationary, the problem of determining the capaci...
Tapas K. Patra, Joy Kuri, Pavan Nuggehalli
COMSWARE
2007
IEEE
14 years 5 months ago
VillageNet: A low-cost, 802.11-based mesh network for rural regions
— VillageNet is a wireless mesh network that aims to provide low-cost broadband Internet access for rural regions. The cost of building the network is kept low by using off-the-s...
Partha Dutta, Sharad Jaiswal, Debmalya Panigrahi, ...
« Prev « First page 1062 / 1134 Last » Next »