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TVLSI
2010
13 years 2 months ago
Architectural Enhancement and System Software Support for Program Code Integrity Monitoring in Application-Specific Instruction-
Program code in a computer system can be altered either by malicious security attacks or by various faults in microprocessors. At the instruction level, all code modifications are ...
Hai Lin, Yunsi Fei, Xuan Guan, Zhijie Jerry Shi
HIPEAC
2007
Springer
13 years 11 months ago
Customizing the Datapath and ISA of Soft VLIW Processors
In this paper, we examine the trade-offs in performance and area due to customizing the datapath and instruction set architecture of a soft VLIW processor implemented in a high-den...
Mazen A. R. Saghir, Mohamad El-Majzoub, Patrick Ak...
ASPDAC
2005
ACM
91views Hardware» more  ASPDAC 2005»
14 years 1 months ago
Efficiently generating test vectors with state pruning
- This paper extends the depth first search (DFS) used in the previously proposed witness string method for generating efficient test vectors. A state pruning method is added that ...
Ying Chen, Dennis Abts, David J. Lilja
ARCS
2009
Springer
14 years 2 months ago
Empirical Performance Models for Java Workloads
Abstract. Java is widely deployed on a variety of processor architectures. Consequently, an understanding of microarchitecture level Java performance is critical to optimize curren...
Pradeep Rao, Kazuaki Murakami
APCSAC
2005
IEEE
14 years 1 months ago
The Challenges of Massive On-Chip Concurrency
Moore’s law describes the growth in on-chip transistor density, which doubles every 18 to 24 months and looks set to continue for at least a decade and possibly longer. This grow...
Kostas Bousias, Chris R. Jesshope