230 search results - page 22 / 46 » PPM Reduction on Embedded Memories in System on Chip |
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
— Traditional level-one instruction caches and data caches for embedded systems typically have the same capacities. Configurable caches either shut down a part of the cache to su...
CODES
2000
IEEE
13 years 12 months ago
2000
IEEE
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve hi...
FPL
2006
Springer
13 years 11 months ago
2006
Springer
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
ICIP
2009
IEEE
13 years 5 months ago
2009
IEEE
Skew-corrected document images are necessary for subsequent downstream operations such as archiving, printing or improving OCR performance. Image rotation is a necessary and more ...
SAC
2009
ACM
14 years 2 months ago
2009
ACM
File systems make use of part of DRAM as the buffer cache to enhance its performance in traditional systems. In this paper, we consider the use of Non-Volatile RAM (NVRAM) as a w...