Sciweavers

66 search results - page 6 / 14
» Packet Delay-Aware Scheduling in Input Queued Switches
Sort
View
ISCAPDCS
2004
13 years 8 months ago
A New Multicast Queuing Mechanism for High-Speed Packet Switches
Increasing multimedia applications such as teleconferencing and video-on-demand require the Internet to effectively provide high-performance multicast support. One of the promisin...
Min Song, Sachin Shetty, Mansoor Alam, HouJun Yang
ICPP
2007
IEEE
14 years 1 months ago
RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management
As the number of computing and storage nodes keeps increasing, the interconnection network is becoming a key element of many computing and communication systems, where the overall...
Gaspar Mora, Pedro Javier García, Jose Flic...
IPPS
1998
IEEE
13 years 11 months ago
HIPIQS: A High-Performance Switch Architecture Using Input Queuing
Switch-based interconnects are used in a number of application domains including parallel system interconnects, local area networks, and wide area networks. However, very few swit...
Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. P...
IFIP
2004
Springer
14 years 2 days ago
The Inherent Queuing Delay of Parallel Packet Switches
The parallel packet switch (PPS) extends the inverse multiplexing architecture, and is extensively used as the core of contemporary commercial switches. A key factor in the perfor...
Hagit Attiya, David Hay
HOTI
2005
IEEE
14 years 9 days ago
Addressing Queuing Bottlenecks at High Speeds
Modern routers and switch fabrics can have hundreds of input and output ports running at up to 10 Gb/s; 40 Gb/s systems are starting to appear. At these rates, the performance of ...
Sailesh Kumar, Jonathan S. Turner, Patrick Crowley