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TVLSI
2008
108views more  TVLSI 2008»
13 years 7 months ago
Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel
To satisfy the advanced forward-error-correction (FEC) standards, in which the Convolutional code and Turbo code may co-exit, a prototype design of a unified Convolutional/Turbo de...
Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu
LCTRTS
2010
Springer
13 years 5 months ago
Translating concurrent action oriented specifications to synchronous guarded actions
Concurrent Action-Oriented Specifications (CAOS) model the behavior of a synchronous hardware circuit as asynchronous guarded at an abstraction level higher than the Register Tran...
Jens Brandt, Klaus Schneider, Sandeep K. Shukla
MICRO
1997
IEEE
141views Hardware» more  MICRO 1997»
13 years 11 months ago
Unroll-and-Jam Using Uniformly Generated Sets
Modern architectural trends in instruction-level parallelism (ILP) are to increase the computational power of microprocessors significantly. As a result, the demands on memory ha...
Steve Carr, Yiping Guan
SC
1993
ACM
13 years 11 months ago
Solving the Boltzmann equation at 61 gigaflops on a 1024-node CM-5
This paper documents the use of a massively parallel computer, specifically the Connection Machine CM-5, to solve the Boltzmann equation to model one-dimensional shock wave struct...
Lyle N. Long, Jacek Myczkowski
CASES
2007
ACM
13 years 11 months ago
Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs
Advances in semiconductor technologies have placed MPSoCs center stage as a standard architecture for embedded applications of ever increasing complexity. Efficient utilization of...
Chengmo Yang, Alex Orailoglu