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ISCA
1997
IEEE
96views Hardware» more  ISCA 1997»
14 years 1 months ago
DataScalar Architectures
DataScalar architectures improve memory system performance by running computation redundantly across multiple processors, which are each tightly coupled with an associated memory....
Doug Burger, Stefanos Kaxiras, James R. Goodman
ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
14 years 27 days ago
Tempest and Typhoon: User-Level Shared Memory
Future parallel computers must efficiently execute not only hand-coded applications but also programs written in high-level, parallel programming languages. Today's machines ...
Steven K. Reinhardt, James R. Larus, David A. Wood
ASAP
2010
IEEE
143views Hardware» more  ASAP 2010»
13 years 11 months ago
Loop transformations for interface-based hierarchies IN SDF graphs
Data-flow has proven to be an attractive computation model for programming digital signal processing (DSP) applications. A restricted version of data-flow, termed synchronous data...
Jonathan Piat, Shuvra S. Bhattacharyya, Mickaë...
BIOSYSTEMS
2007
92views more  BIOSYSTEMS 2007»
13 years 9 months ago
A phase-based stereo vision system-on-a-chip
A simple and fast technique for depth estimation based on phase measurement has been adopted for the implementation of a real-time stereo system with sub-pixel resolution on an FP...
Javier Díaz, Eduardo Ros, Silvio P. Sabatin...
CVGIP
2004
169views more  CVGIP 2004»
13 years 9 months ago
Contour interpolation by straight skeletons
In this paper we present an efficient method for interpolating a piecewise-linear surface between two parallel slices, each consisting of an arbitrary number of (possibly nested) ...
Gill Barequet, Michael T. Goodrich, Aya Levi-Stein...