Sciweavers

5424 search results - page 1064 / 1085
» Parallel Computing with FPGAs - Concepts and Applications
Sort
View
IEEEPACT
2006
IEEE
14 years 1 months ago
Architectural support for operating system-driven CMP cache management
The role of the operating system (OS) in managing shared resources such as CPU time, memory, peripherals, and even energy is well motivated and understood [23]. Unfortunately, one...
Nauman Rafique, Won-Taek Lim, Mithuna Thottethodi
IEEEPACT
2006
IEEE
14 years 1 months ago
Two-level mapping based cache index selection for packet forwarding engines
Packet forwarding is a memory-intensive application requiring multiple accesses through a trie structure. The efficiency of a cache for this application critically depends on the ...
Kaushik Rajan, Ramaswamy Govindarajan
RTSS
2006
IEEE
14 years 1 months ago
Run-Time Services for Hybrid CPU/FPGA Systems on Chip
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
Jason Agron, Wesley Peck, Erik Anderson, David L. ...
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
14 years 24 days ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...
COCOON
1998
Springer
13 years 11 months ago
The Colored Sector Search Tree: A Dynamic Data Structure for Efficient High Dimensional Nearest-Foreign-Neighbor Queries
Abstract. In this paper we present the new data structure Colored Sector Search Tree (CSST ) for solving the Nearest-Foreign-Neighbor Query Problem (NFNQP ): Given a set S of n col...
Thomas Graf, V. Kamakoti, N. S. Janaki Latha, C. P...
« Prev « First page 1064 / 1085 Last » Next »