In previous papers [5,6], an optical switch architecture was proposed to handle variable-length packets such as IP datagrams, based on an AWG device to route packets and equipped w...
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Aimed to provide computation ubiquitously, pervasive computing is perceived as a means to provide an user the transparency of anywhere, anyplace, anytime computing. Pervasive comp...
K. Kalapriya, S. K. Nandy, V. Satish, R. Uma Mahes...
Several new Complex Event Processing (CEP) engines have been recently released, many of which are intended to be used in performance sensitive scenarios - like fraud detection, tr...
Marcelo R. N. Mendes, Pedro Bizarro, Paulo Marques
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
Isil Oz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir...