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HPCA
2001
IEEE
16 years 2 months ago
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
SIGMOD
2003
ACM
150views Database» more  SIGMOD 2003»
16 years 2 months ago
Capturing both Types and Constraints in Data Integration
We propose a framework for integrating data from multiple relational sources into an XML document that both conforms to a given DTD and satisfies predefined XML constraints. The f...
Michael Benedikt, Chee Yong Chan, Wenfei Fan, Juli...
137
Voted
ISORC
2007
IEEE
15 years 8 months ago
Evaluating Real-Time Publish/Subscribe Service Integration Approaches in QoS-Enabled Component Middleware
As quality of service (QoS)-enabled component middleware technologies gain widespread acceptance to build distributed real-time and embedded (DRE) systems, it becomes necessary fo...
Gan Deng, Ming Xiong, Aniruddha S. Gokhale, George...
ARVLSI
1997
IEEE
151views VLSI» more  ARVLSI 1997»
15 years 6 months ago
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...
Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun
108
Voted
SERP
2003
15 years 3 months ago
Integrated Tools for Performance-Oriented Distributed Software Development
This paper presents an integrated set of tools for performance-oriented development of software targeted to distributed heterogeneous systems. Using these tools, software developm...
Nicola Mazzocca, Emilio Mancini, Massimiliano Rak,...