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POPL
2009
ACM
14 years 9 months ago
Feedback-directed barrier optimization in a strongly isolated STM
Speed improvements in today's processors have largely been delivered in the form of multiple cores, increasing the importance of ions that ease parallel programming. Software...
Nathan Grasso Bronson, Christos Kozyrakis, Kunle O...
VLSID
2009
IEEE
177views VLSI» more  VLSID 2009»
14 years 9 months ago
Accelerating System-Level Design Tasks Using Commodity Graphics Hardware: A Case Study
Many system-level design tasks (e.g. timing analysis, hardware/software partitioning and design space exploration) involve computational kernels that are intractable (usually NP-ha...
Unmesh D. Bordoloi, Samarjit Chakraborty
SAS
2009
Springer
162views Formal Methods» more  SAS 2009»
14 years 9 months ago
Interval Polyhedra: An Abstract Domain to Infer Interval Linear Relationships
Polyhedra: An Abstract Domain to Infer Interval Linear Relationships Liqian Chen1,2 , Antoine Min?e2,3 , Ji Wang1 , and Patrick Cousot2,4 1 National Laboratory for Parallel and Dis...
Antoine Miné, Ji Wang, Liqian Chen, Patrick...
HPCA
2009
IEEE
14 years 9 months ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...
HPCA
2009
IEEE
14 years 9 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
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