Sciweavers

1138 search results - page 181 / 228
» Parallel Implementation of Constraint Solving
Sort
View
HPCA
2012
IEEE
12 years 4 months ago
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chi
Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
Timothy N. Miller, Xiang Pan, Renji Thomas, Naser ...
CW
2002
IEEE
14 years 1 months ago
Beyond Flat Panning and Zooming: Dolly-Enhanced SQTVR
This paper describes a novel solution to problems associated with interactive display of immersive stereographic imagery via Apple’s QuickTime Virtual Reality (QTVR) technology....
N. A. Bolhassan, William L. Martens, Michael M. Co...
ICIP
2001
IEEE
14 years 10 months ago
Directed acyclic graph based mode optimization for H.263 video encoding
Optimal mode selection for video coding is important in minimizing visual distortion given a rate constraint, and it has been studied in the literature using a single previous mac...
G. Cheung
SAS
2005
Springer
118views Formal Methods» more  SAS 2005»
14 years 2 months ago
Inference of Well-Typings for Logic Programs with Application to Termination Analysis
A method is developed to infer a polymorphic well-typing for a logic program. Our motivation is to improve the automation of termination analysis by deriving types from which norms...
Maurice Bruynooghe, John P. Gallagher, Wouter Van ...
DFT
2003
IEEE
113views VLSI» more  DFT 2003»
14 years 2 months ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...