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CJ
2006
84views more  CJ 2006»
13 years 7 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
IPPS
2003
IEEE
14 years 1 months ago
Exploring the Predictability of MPI Messages
Scalability to large number of processes is one of the weaknesses of current MPI implementations. Standard implementations are able to scale to hundreds of nodes, but no beyond th...
Felix Freitag, Jordi Caubet, Montse Farreras, Toni...
ICS
2009
Tsinghua U.
14 years 2 months ago
QuakeTM: parallelizing a complex sequential application using transactional memory
“Is transactional memory useful?” is the question that cannot be answered until we provide substantial applications that can evaluate its capabilities. While existing TM appli...
Vladimir Gajinov, Ferad Zyulkyarov, Osman S. Unsal...
IEEEPACT
2009
IEEE
14 years 2 months ago
Interprocedural Load Elimination for Dynamic Optimization of Parallel Programs
Abstract—Load elimination is a classical compiler transformation that is increasing in importance for multi-core and many-core architectures. The effect of the transformation is ...
Rajkishore Barik, Vivek Sarkar
PC
2012
223views Management» more  PC 2012»
12 years 3 months ago
Using shared arrays in message-driven parallel programs
This paper describes a safe and efficient combination of the object-based message-driven execution and shared array parallel programming models. In particular, we demonstrate how ...
Phil Miller, Aaron Becker, Laxmikant V. Kalé...