Sciweavers

309 search results - page 15 / 62
» Parallel Memory Architecture for Arbitrary Stride Accesses
Sort
View
145
Voted
SC
2000
ACM
15 years 8 months ago
Performance of Hybrid Message-Passing and Shared-Memory Parallelism for Discrete Element Modeling
The current trend in HPC hardware is towards clusters of shared-memory (SMP) compute nodes. For applications developers the major question is how best to program these SMP cluster...
D. S. Henty
153
Voted
IPPS
2010
IEEE
15 years 27 days ago
Efficient hardware support for the Partitioned Global Address Space
We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory...
Holger Fröning, Heiner Litz
119
Voted
IEEEPACT
1998
IEEE
15 years 7 months ago
Athapascan-1: On-Line Building Data Flow Graph in a Parallel Language
In order to achieve practical efficient execution on a parallel architecture, a knowledge of the data dependencies related to the application appears as the key point for building...
François Galilée, Jean-Louis Roch, G...
121
Voted
HIPS
1998
IEEE
15 years 8 months ago
Implementing Automatic Coordination on Networks of Workstations
Distributed shared objects are a well known approach to achieve independenceof the memory model for parallel programming. The illusion of shared (global) objects is a conabstracti...
Christian Weiß, Jürgen Knopp, Hermann H...
108
Voted
IPPS
1999
IEEE
15 years 8 months ago
NWCache: Optimizing Disk Accesses via an Optical Network/Write Cache Hybrid
In this paper we propose a simple extension to the I/O architecture of scalable multiprocessors that optimizes page swap-outs significantly. More specifically, we propose the use o...
Enrique V. Carrera, Ricardo Bianchini