309 search results - page 16 / 62 » Parallel Memory Architecture for Arbitrary Stride Accesses |
ASPLOS
2010
ACM
14 years 11 days ago
2010
ACM
Heterogeneous computing combines general purpose CPUs with accelerators to efficiently execute both sequential control-intensive and data-parallel phases of applications. Existin...
ARVLSI
1997
IEEE
13 years 11 months ago
1997
IEEE
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...
ISSS
1996
IEEE
13 years 11 months ago
1996
IEEE
In this paper we present the problem of flow graph balancing for minimizingthe required memory bandwidth. Our goal is to minimize the required memory bandwidth within the given cy...
IPPS
2002
IEEE
14 years 14 days ago
2002
IEEE
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...
WMPI
2004
ACM
14 years 29 days ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...