309 search results - page 31 / 62 » Parallel Memory Architecture for Arbitrary Stride Accesses |
SIGMOD
2010
ACM
13 years 2 months ago
2010
ACM
This demonstration presents Crescando, an implementation of a distributed relational table that guarantees predictable response time on unpredictable workloads. In Crescando, data...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
MICRO
1998
IEEE
13 years 12 months ago
1998
IEEE
Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are p...
SIGGRAPH
1994
ACM
13 years 11 months ago
1994
ACM
FBRAM, a new form of dynamic random access memory that greatly accelerates the rendering of Z-buffered primitives, is presented. Two key concepts make this acceleration possible. ...
ICPP
2009
IEEE
14 years 2 months ago
2009
IEEE
—Sparse Matrix-Vector multiplication (SpMV) is a very challenging computational kernel, since its performance depends greatly on both the input matrix and the underlying architec...