309 search results - page 35 / 62 » Parallel Memory Architecture for Arbitrary Stride Accesses |
EGC
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. We describe the idea of a Science Gateway, an applicationspeciļ¬c task wrapped as a web service, and some examples of these that are being implemented on the US TeraGrid...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
The continued scaling of device dimensions and the operating voltage reduces the critical charge and thus natural noise tolerance level of transistors. As a result, circuits can p...
IPPS
2002
IEEE
14 years 15 days ago
2002
IEEE
This paper introduces semi-user-level communication architecture, a new high-performance light-weighted communication architecture for inter-node communication of clusters. Differ...
HIPC
2009
Springer
13 years 5 months ago
2009
Springer
In many-core architectures, memory blocks are commonly assigned to the banks of a NUCA cache by following a physical mapping. This mapping assigns blocks to cache banks in a round-...
EGH
2010
Springer
13 years 5 months ago
2010
Springer
This paper proposes a massively parallel hardware architecture for efficient tracing of incoherent rays, e.g. for global illumination. The general approach is centered around hier...