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» Parallel Memory Architecture for Arbitrary Stride Accesses
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ICDCS
2009
IEEE
14 years 4 months ago
Reducing Disk I/O Performance Sensitivity for Large Numbers of Sequential Streams
Retrieving sequential rich media content from modern commodity disks is a challenging task. As disk capacity increases, there is a need to increase the number of streams that are ...
George Panagiotakis, Michail Flouris, Angelos Bila...
GLVLSI
2011
IEEE
344views VLSI» more  GLVLSI 2011»
12 years 11 months ago
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
Azam Seyedi, Adrià Armejach, Adrián ...
HPCA
2008
IEEE
14 years 7 months ago
Automated microprocessor stressmark generation
Estimating the maximum power and thermal characteristics of a processor is essential for designing its power delivery system, packaging, cooling, and power/thermal management sche...
Ajay M. Joshi, Lieven Eeckhout, Lizy Kurian John, ...
SI3D
1995
ACM
13 years 11 months ago
Real-Time Programmable Shading
One of the main techniques used by software renderers to produce stunningly realistic images is programmable shading—executing an arbitrarily complex program to compute the colo...
Anselmo Lastra, Steven Molnar, Marc Olano, Yulan W...
WWW
2007
ACM
14 years 8 months ago
GigaHash: scalable minimal perfect hashing for billions of urls
A minimal perfect function maps a static set of keys on to the range of integers {0,1,2, ... , - 1}. We present a scalable high performance algorithm based on random graphs for ...
Kumar Chellapilla, Anton Mityagin, Denis Xavier Ch...