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» Parallel Memory Architecture for Arbitrary Stride Accesses
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TVCG
2012
182views Hardware» more  TVCG 2012»
11 years 10 months ago
ISP: An Optimal Out-of-Core Image-Set Processing Streaming Architecture for Parallel Heterogeneous Systems
—Image population analysis is the class of statistical methods that plays a central role in understanding the development, evolution and disease of a population. However, these t...
Linh K. Ha, Jens Krüger, João Luiz Dih...
FPL
2000
Springer
119views Hardware» more  FPL 2000»
13 years 11 months ago
A Self-Reconfigurable Gate Array Architecture
Abstract. This paper presents an innovative architecture for a reconfigurable device that allows single cycle context switching and single cycle random access to the unified on-chi...
Reetinder P. S. Sidhu, Sameer Wadhwa, Alessandro M...
CF
2010
ACM
14 years 17 days ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
PDP
2011
IEEE
12 years 11 months ago
Accelerating Parameter Sweep Applications Using CUDA
—This paper proposes a parallelization scheme for parameter sweep (PS) applications using the compute unified device architecture (CUDA). Our scheme focuses on PS applications w...
Masaya Motokubota, Fumihiko Ino, Kenichi Hagihara
ISCA
1995
IEEE
118views Hardware» more  ISCA 1995»
13 years 11 months ago
The EM-X Parallel Computer: Architecture and Basic Performance
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Ha...