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121
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DATE
2005
IEEE
187views Hardware» more  DATE 2005»
15 years 7 months ago
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
In this paper, the application of a cycle accurate binary translator for rapid prototyping of SoCs will be presented. This translator generates code to run on a rapid prototyping ...
Jürgen Schnerr, Oliver Bringmann, Wolfgang Ro...
VTC
2006
IEEE
15 years 8 months ago
Group-Based Linear Parallel Interference Cancellation for DS-CDMA Systems
— The increase in the demand for voice and data wireless services creates a need for a more efficient use of the available bandwidth. Current and future generations cellular sys...
Benoit Pelletier, Benoît Champagne
ICPPW
2003
IEEE
15 years 7 months ago
Parallelization of Cellular Neural Networks for Image Processing on Cluster Architectures
In this paper a simple but effective approach for parallelization of cellular neural networks for image processing is developed. Digital gray-scale images were used to evaluate th...
Thomas Weishäupl, Erich Schikuta
118
Voted
IPPS
2000
IEEE
15 years 6 months ago
A Requirements Analysis for Parallel KDD Systems
Abstract. The current generation of data mining tools have limited capacity and performance, since these tools tend to be sequential. This paper explores a migration path out of th...
William Maniatty, Mohammed Javeed Zaki
FPL
2008
Springer
92views Hardware» more  FPL 2008»
15 years 3 months ago
Parallel hardware objects for dynamically partial reconfiguration
Many of today's software-to-hardware compiler projects try to find dataflow parallelism in a sequential program description and use it to generate parallel running hardware c...
Norbert Abel, Frederik Grüll, Nick Meier, And...