Sciweavers

657 search results - page 83 / 132
» Parallel Parameter Tuning for Applications with Performance ...
Sort
View
CLUSTER
2009
IEEE
14 years 1 months ago
Finding a tradeoff between host interrupt load and MPI latency over Ethernet
—Achieving high-performance message passing on top of generic ETHERNET hardware suffers from the NIC interruptdriven model where coalescing is usually involved. We present an in-...
Brice Goglin, Nathalie Furmento
AROBOTS
2000
108views more  AROBOTS 2000»
13 years 8 months ago
Robot Awareness in Cooperative Mobile Robot Learning
Most of the straight-forward learning approaches in cooperative robotics imply for each learning robot a state space growth exponential in the number of team members. To remedy the...
Claude F. Touzet
JPDC
2000
141views more  JPDC 2000»
13 years 8 months ago
A System for Evaluating Performance and Cost of SIMD Array Designs
: SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem ...
Martin C. Herbordt, Jade Cravy, Renoy Sam, Owais K...
ASPLOS
2006
ACM
14 years 16 days ago
Instruction scheduling for a tiled dataflow architecture
This paper explores hierarchical instruction scheduling for a tiled processor. Our results show that at the top level of the hierarchy, a simple profile-driven algorithm effective...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
ICCV
2009
IEEE
13 years 6 months ago
SCRAMSAC: Improving RANSAC's efficiency with a spatial consistency filter
Geometric verification with RANSAC has become a crucial step for many local feature based matching applications. Therefore, the details of its implementation are directly relevant...
Torsten Sattler, Bastian Leibe, Leif Kobbelt