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ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
14 years 2 months ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
HPCA
2003
IEEE
14 years 9 months ago
Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors
Thread-level speculation provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or specul...
María Jesús Garzarán, Milos P...
IPPS
2008
IEEE
14 years 3 months ago
A plug-and-play model for evaluating wavefront computations on parallel architectures
This paper develops a plug-and-play reusable LogGP model that can be used to predict the runtime and scaling behavior of different MPI-based pipelined wavefront applications runni...
Gihan R. Mudalige, Mary K. Vernon, Stephen A. Jarv...
IPPS
2006
IEEE
14 years 2 months ago
A simulator for parallel applications with dynamically varying compute node allocation
Dynamically allocating computing nodes to parallel applications is a promising technique for improving the utilization of cluster resources. We introduce the concept of dynamic ef...
Basile Schaeli, B. Gerlach, Roger D. Hersch
IPPS
1996
IEEE
14 years 22 days ago
A Method for Register Allocation to Loops in Multiple Register File Architectures
Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocat...
David J. Kolson, Alexandru Nicolau, Nikil D. Dutt,...