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» Parallel Processing Architectures for Reconfigurable Systems
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IPPS
2003
IEEE
14 years 29 days ago
Performance and Overhead in a Hybrid Reconfigurable Computer
In this paper, we overview general hardware architecture and a programming model of SRC-6ETM reconfigurable computers, and compare the performance of the SRC-6E machine vs. IntelÂ...
Osman Devrim Fidanci, Daniel S. Poznanovic, Kris G...
ACL
2008
13 years 9 months ago
Distributed Listening: A Parallel Processing Approach to Automatic Speech Recognition
While speech recognition systems have come a long way in the last thirty years, there is still room for improvement. Although readily available, these systems are sometimes inaccu...
Yolanda McMillian, Juan E. Gilbert
TPDS
2002
117views more  TPDS 2002»
13 years 7 months ago
Gemini: An Optical Interconnection Network for Parallel Processing
Abstract--The Gemini interconnect is a dual technology (optical and electrical) interconnection network designed for use in tightlycoupled multicomputer systems. It consists of a c...
Roger D. Chamberlain, Mark A. Franklin, Ch'ng Shi ...
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 11 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan
IEEEHPCS
2010
13 years 2 months ago
XPSoC: A reconfigurable solution for multimedia contents protection
Network Multimedia data also need to be encrypted to protect private content and access control. Considering performance constraints and embedded system issues, many hardware solu...
Linfeng Ye, Jean-Philippe Diguet, Guy Gogniat