Sciweavers

833 search results - page 50 / 167
» Parallel Processing Architectures for Reconfigurable Systems
Sort
View
EUROCRYPT
2000
Springer
14 years 17 days ago
Cox-Rower Architecture for Fast Parallel Montgomery Multiplication
Abstract. This paper proposes a fast parallel Montgomery multiplication algorithm based on Residue Number Systems (RNS). It is easy to construct a fast modular exponentiation by ap...
Shin-ichi Kawamura, Masanobu Koike, Fumihiko Sano,...
ASAP
2000
IEEE
125views Hardware» more  ASAP 2000»
14 years 1 months ago
High Level Modeling for Parallel Executions of Nested Loop Algorithms
High level modeling and (quantitative) performance analysis of signal processing systems requires high level models for the applications(algorithms) and the implementations (archi...
Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, B...
DAC
2002
ACM
14 years 10 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
PDIS
1991
IEEE
14 years 14 days ago
Practical Prefetching Techniques for Parallel File Systems
Improvements in the processing speed of multiprocessors are outpacing improvements in the speed of disk hardware. Parallel disk I/O subsystems have been proposed as one way to clo...
David Kotz, Carla Schlatter Ellis
IPPS
2002
IEEE
14 years 1 months ago
Real-Time Communication for Distributed Vision Processing Based on Imprecise Computation Model
In this paper we propose an efficient real-time communication mechanism for distributed vision processing. One of the biggest problems of distributed vision processing, as is the ...
Hiromasa Yoshimoto, Daisaku Arita, Rin-ichiro Tani...