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» Parallel Processing Architectures for Reconfigurable Systems
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VLSISP
2008
147views more  VLSISP 2008»
13 years 7 months ago
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critica...
Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sun...
ENTCS
2008
106views more  ENTCS 2008»
13 years 9 months ago
Modelling Adaptive Systems in ForSyDe
Emerging architectures such as partially reconfigurable FPGAs provide a huge potential for adaptivity in the area of embedded systems. Since many system functions are only execute...
Ingo Sander, Axel Jantsch
DATE
2009
IEEE
138views Hardware» more  DATE 2009»
14 years 3 months ago
Hardware/software co-design architecture for thermal management of chip multiprocessors
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
Omer Khan, Sandip Kundu
FPL
2009
Springer
102views Hardware» more  FPL 2009»
14 years 1 months ago
Macs: A Minimal Adaptive routing circuit-switched architecture for scalable and parametric NoCs
Networks-on-Chips (NoCs) are an emerging communication topology paradigm in single chip VLSI design, enhancing parallelism and system scalability. Processing units (PUs) connect t...
Rohit Kumar, Ann Gordon-Ross
VIP
2001
13 years 10 months ago
Image Segmentation on Spiral Architecture
Spiral Architecture is a relatively new and powerful approach to general purpose machine vision system. It contains very useful geometric and algebraic properties. Two algebraic o...
Qiang Wu, Xiangjian He, Tom Hintz