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» Parallel Skyline Computation on Multicore Architectures
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HIPC
2007
Springer
14 years 1 months ago
qTLB: Looking Inside the Look-Aside Buffer
Rapid evolution of multi-core platforms is putting additional stress on shared processor resources like TLB. TLBs have mostly been private resources for the application running on ...
Omesh Tickoo, Hari Kannan, Vineet Chadha, Ramesh I...
SPAA
2010
ACM
14 years 16 days ago
Simplifying concurrent algorithms by exploiting hardware transactional memory
We explore the potential of hardware transactional memory (HTM) to improve concurrent algorithms. We illustrate a number of use cases in which HTM enables significantly simpler c...
Dave Dice, Yossi Lev, Virendra J. Marathe, Mark Mo...
IPPS
2007
IEEE
14 years 2 months ago
A Comprehensive Analysis of OpenMP Applications on Dual-Core Intel Xeon SMPs
Hybrid chip multithreaded SMPs present new challenges as well as new opportunities to maximize performance. Our intention is to discover the optimal operating configuration of suc...
Ryan E. Grant, Ahmad Afsahi
ISBI
2007
IEEE
14 years 2 months ago
Real-Time Mutual-Information-Based Linear Registration on the Cell Broadband Engine Processor
Emerging multi-core processors are able to accelerate medical imaging applications by exploiting the parallelism available in their algorithms. We have implemented a mutual-inform...
Moriyoshi Ohara, Hangu Yeo, Frank Savino, Giridhar...
ASAP
2007
IEEE
95views Hardware» more  ASAP 2007»
14 years 2 months ago
Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router
With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip and multicore architect...
Sumit D. Mediratta, Jeffrey T. Draper