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» Parallel Sorting with Limited Bandwidth
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MSO
2003
13 years 8 months ago
Simulation based Development of Efficient Hardware for Sort based Algorithms
The use of sub-optimal digital systems can at times lead to high speed, efficient, costeffective structures that are sufficient to perform needed tasks. We describe here a system ...
Niklas Hansson, Jay H. Harris
HPCA
1999
IEEE
13 years 11 months ago
Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory
Processor speeds are increasing rapidly, and memory speeds are not keeping up. Streaming computations (such as multi-media or scientific applications) are among those whose perfor...
Sung I. Hong, Sally A. McKee, Maximo H. Salinas, R...
ICPP
2003
IEEE
14 years 22 days ago
Scheduling Algorithms with Bus Bandwidth Considerations for SMPs
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...
Christos D. Antonopoulos, Dimitrios S. Nikolopoulo...
IPPS
2007
IEEE
14 years 1 months ago
Optimizing Sorting with Machine Learning Algorithms
The growing complexity of modern processors has made the development of highly efficient code increasingly difficult. Manually developing highly efficient code is usually expen...
Xiaoming Li, María Jesús Garzar&aacu...
IPPS
1999
IEEE
13 years 11 months ago
Segment Directory Enhancing the Limited Directory Cache Coherence Schemes
We present a new arrangement of directory bits called the segment directory to improve directory storage efficiency: a segment directory can point to several sharing processors wi...
Jong Hyuk Choi, Kyu Ho Park