Sciweavers

224 search results - page 30 / 45
» Parallel Switching in Connection-Oriented Networks
Sort
View
IPPS
2009
IEEE
14 years 2 months ago
Implementing and evaluating multithreaded triad census algorithms on the Cray XMT
Commonly represented as directed graphs, social networks depict relationships and behaviors among social entities such as people, groups, and organizations. Social network analysi...
George Chin Jr., Andrès Márquez, Sut...
HOTI
2002
IEEE
14 years 10 days ago
Architecture and Hardware for Scheduling Gigabit Packet Streams
We present an architecture and hardware for scheduling gigabit packet streams in server clusters that combines a Network Processor datapath and an FPGA for use in server NICs and ...
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten ...
HPCA
1995
IEEE
13 years 11 months ago
Reducing Communication Latency with Path Multiplexing in Optically Interconnected Multiprocessor Systems
—Reducing communication latency, which is a performance bottleneck in optically interconnected multiprocessor systems, is of prominent importance. A conventional approach for est...
Chunming Qiao, Rami G. Melhem
TPDS
2002
105views more  TPDS 2002»
13 years 7 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills
ERSA
2010
172views Hardware» more  ERSA 2010»
13 years 5 months ago
A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
Heiner Giefers, Marco Platzner