52 search results - page 4 / 11 » Parallel VLSI Architectures for Cryptographic Systems |
FCCM
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper presents a hardware-optimized variant of the well-known Gaussian elimination over GF(2) and its highly efficient implementation. The proposed hardware architecture, we...
PACT
2005
Springer
14 years 2 months ago
2005
Springer
Abstract. We use an enhanced operational semantics to infer quantitative measures on systems describing cryptographic protocols. System transitions carry enhanced labels. We assign...
FCCM
2011
IEEE
13 years 10 days ago
2011
IEEE
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
HOTI
2002
IEEE
14 years 1 months ago
2002
IEEE
We present the architecture and practical VLSI implementation of a 4-Tb/s single-stage switch. It is based on a combined input- and crosspoint-queued structure with virtual output...
ARVLSI
1997
IEEE
14 years 5 days ago
1997
IEEE
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...