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MSO
2003
13 years 8 months ago
Simulation based Development of Efficient Hardware for Sort based Algorithms
The use of sub-optimal digital systems can at times lead to high speed, efficient, costeffective structures that are sufficient to perform needed tasks. We describe here a system ...
Niklas Hansson, Jay H. Harris
ICPR
2004
IEEE
14 years 7 months ago
An FPGA-Based Architecture for Real Time Image Feature Extraction
We propose a novel FPGA-based architecture for the extraction of four texture features using Gray Level Cooccurrence Matrix (GLCM) analysis. These features are angular second mome...
Dimitrios E. Maroulis, Dimitrios K. Iakovidis, Dim...
DATE
2007
IEEE
134views Hardware» more  DATE 2007»
14 years 1 months ago
Non-fractional parallelism in LDPC decoder implementations
Because of its excellent bit-error-rate performance, the Low-Density Parity-Check (LDPC) decoding algorithm is gaining increased attention in communication standards and literatur...
John Dielissen, Andries Hekstra
ICIAP
2005
ACM
14 years 7 days ago
Markovian Energy-Based Computer Vision Algorithms on Graphics Hardware
This paper shows how Markovian segmentation algorithms used to solve well known computer vision problems such as motion estimation, motion detection and stereovision can be signi...
Pierre-Marc Jodoin, Max Mignotte, Jean-Franç...
SPAA
2010
ACM
13 years 11 months ago
Simplifying concurrent algorithms by exploiting hardware transactional memory
We explore the potential of hardware transactional memory (HTM) to improve concurrent algorithms. We illustrate a number of use cases in which HTM enables significantly simpler c...
Dave Dice, Yossi Lev, Virendra J. Marathe, Mark Mo...