462 search results - page 24 / 93 » Parallel algorithm for hardware implementation of inverse ha... |
ISCAS
2003
IEEE
14 years 19 days ago
2003
IEEE
In this paper, we propose a fast pipeline VLSI architecture for 1D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predict...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
To address the problem of performing long time simulations of biochemical pathways under in vivo cellular conditions, we have developed a lattice-based, reaction-diffusion model t...
IEEEPACT
2008
IEEE
14 years 1 months ago
2008
IEEE
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
SASP
2009
IEEE
14 years 2 months ago
2009
IEEE
—This paper describes a multi-threaded parallel design and implementation of the Smith-Waterman (SM) algorithm on compute unified device architecture (CUDA)-compatible graphic pr...
ERSA
2007
13 years 8 months ago
2007
Molecular Dynamics simulations have become an interesting target for acceleration using Field-Programmable Gate Arrays (FPGA). Still to be attempted completely in FPGA hardware is...