Sciweavers

462 search results - page 3 / 93
» Parallel algorithm for hardware implementation of inverse ha...
Sort
View
FCCM
2006
IEEE
195views VLSI» more  FCCM 2006»
14 years 19 days ago
A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)
This paper presents a hardware-optimized variant of the well-known Gaussian elimination over GF(2) and its highly efficient implementation. The proposed hardware architecture, we...
Andrey Bogdanov, M. C. Mertens
EUROPAR
2007
Springer
14 years 23 days ago
Hirschberg's Algorithm on a GCA and Its Parallel Hardware Implementation
We present in detail a GCA (Global Cellular Automaton) algorithm with 3n cells for Hirschberg’s algorithm which determines the connected components of a n-node undirected graph w...
Johannes Jendrsczok, Rolf Hoffmann, Jörg Kell...
JPDC
2006
111views more  JPDC 2006»
13 years 6 months ago
Designing irregular parallel algorithms with mutual exclusion and lock-free protocols
Irregular parallel algorithms pose a significant challenge for achieving high performance because of the difficulty predicting memory access patterns or execution paths. Within an...
Guojing Cong, David A. Bader
FCCM
2005
IEEE
124views VLSI» more  FCCM 2005»
14 years 6 days ago
Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA
The CLA-EC is a model obtained by combining the concepts of cellular learning automata and evolutionary algorithms. The parallel structure of the CLA-EC makes it suitable for hard...
Arash Hariri, Reza Rastegar, Morteza Saheb Zamani,...