Sciweavers

462 search results - page 52 / 93
» Parallel algorithm for hardware implementation of inverse ha...
Sort
View
IPPS
2010
IEEE
13 years 8 months ago
Overlapping computation and communication: Barrier algorithms and ConnectX-2 CORE-Direct capabilities
Abstract--This paper explores the computation and communication overlap capabilities enabled by the new CORE-Direct hardware capabilities introduced in the InfiniBand (IB) Host Cha...
Richard L. Graham, Stephen W. Poole, Pavel Shamis,...
ATS
2001
IEEE
126views Hardware» more  ATS 2001»
14 years 2 months ago
Design of an Optimal Test Access Architecture Using a Genetic Algorithm
Test access is a major problem for core-based systemon-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms...
Zahra Sadat Ebadi, André Ivanov
CGO
2004
IEEE
14 years 2 months ago
Custom Data Layout for Memory Parallelism
In this paper, we describe a generalized approach to deriving a custom data layout in multiple memory banks for array-based computations, to facilitate high-bandwidth parallel mem...
Byoungro So, Mary W. Hall, Heidi E. Ziegler
ASAP
2007
IEEE
111views Hardware» more  ASAP 2007»
14 years 5 months ago
Entropy Coding on a Programmable Processor Array for Multimedia SoC
Entropy encoding and decoding is a crucial part of any multimedia system that can be highly demanding in terms of computing power. Hardware implementation of typical compression a...
Roberto R. Osorio, Javier D. Bruguera
JGTOOLS
2006
199views more  JGTOOLS 2006»
13 years 10 months ago
Fast Approximation of High-Order Voronoi Diagrams and Distance Transforms on the GPU
We present a graphics hardware implementation of the tangent-plane algorithm for computing the kth-order Voronoi diagram of a set of point sites in image space. Correct and effici...
Ian Fischer, Craig Gotsman