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ISCAS
2005
IEEE
143views Hardware» more  ISCAS 2005»
14 years 9 days ago
Design and FPGA implementation of a structure of evolutionary digital filters for hardware implementation
— In this paper, we design and implement an improved hardware-based evolutionary digital filter (EDF) version 2. The EDF is an adaptive digital filter which is controlled by ad...
Masahide Abe, Hiroki Arai, Masayuki Kawamata
ASAP
2008
IEEE
135views Hardware» more  ASAP 2008»
14 years 1 months ago
On the high-throughput implementation of RIPEMD-160 hash algorithm
Miroslav Knezevic, Kazuo Sakiyama, Yong Ki Lee, In...
IAJIT
2006
145views more  IAJIT 2006»
13 years 6 months ago
Fast 160-Bits GF (P) Elliptic Curve Crypto Hardware of High-Radix Scalable Multipliers
In this paper, a fast hardware architecture for elliptic curve cryptography computation in Galois Field GF(p) is proposed. The architecture is implemented for 160-bits, as its dat...
Adnan Abdul-Aziz Gutub
TOMS
2008
120views more  TOMS 2008»
13 years 6 months ago
Families of algorithms related to the inversion of a Symmetric Positive Definite matrix
We present families of algorithms for operations related to the computation of the inverse of a Symmetric Positive Definite (SPD) matrix: Cholesky factorization, inversion of a tr...
Paolo Bientinesi, Brian C. Gunter, Robert A. van d...
FPL
2008
Springer
120views Hardware» more  FPL 2008»
13 years 8 months ago
An FPGA-based implementation of the MINRES algorithm
Due to continuous improvements in the resources available on FPGAs, it is becoming increasingly possible to accelerate floating point algorithms. The solution of a system of linea...
David Boland, George A. Constantinides