462 search results - page 90 / 93 » Parallel algorithm for hardware implementation of inverse ha... |
DAC
2002
ACM
14 years 8 months ago
2002
ACM
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
FMICS
2007
Springer
14 years 1 months ago
2007
Springer
Message passing using libraries implementing the Message Passing Interface (MPI) standard is the dominant communication mechanism in high performance computing (HPC) applications. ...
VLDB
2005
ACM
14 years 24 days ago
2005
ACM
In this paper, we examine the performance of frequent pattern mining algorithms on a modern processor. A detailed performance study reveals that even the best frequent pattern min...
HPCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
IEEEPACT
2008
IEEE
14 years 1 months ago
2008
IEEE
While technology trends have ushered in the age of chip multiprocessors (CMP) and enabled designers to place an increasing number of cores on chip, a fundamental question is what ...