63 search results - page 9 / 13 » Parallel algorithms for inductance extraction of VLSI circui... |
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents an efficient modeling scheme and a partitioning heuristic for parallelizing VLSI post-placement timing optimization. Encoding the paths with timing violations...
GLVLSI
2003
IEEE
14 years 21 days ago
2003
IEEE
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
DFT
2007
IEEE
14 years 1 months ago
2007
IEEE
Many side-channel attacks on implementations of cryptographic algorithms have been developed in recent years demonstrating the ease of extracting the secret key. In response, vari...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
We present the first efficient approach to global routing that takes spacing-dependent costs into account and provably finds a near-optimum solution including these costs. We sh...
JCP
2007
13 years 7 months ago
2007
— Presented in this paper is a joint algorithm optimization and architecture design framework for analysis of repetitive regularities. Two closely coupled algorithm optimization ...