Optimizing yield in global routing

We present the first efficient approach to global routing that takes spacing-dependent costs into account and provably finds a near-optimum solution including these costs. We show that this algorithm can be used to optimize manufacturing yield. The core routine is a parallelized fully polynomial approximation scheme, scaling very well with the number of processors. We present results showing that our algorithm reduces the expected number of defects in wiring by more than 10 percent on state-of-the-art industrial chips. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids—Placement and Routing; G.2.2 [Discrete Mathematics]: Graph Theory— Graph Algorithms, Network Problems General Terms Algorithms Keywords Multi-commodity flows, Steiner tree packing, VLSI routing, yield optimization

• Type: Conference
• Year: 2006
• Where: ICCAD
• Authors: Dirk Müller
• Keywords: Global Routing, Hardware, ICCAD 2006, Polynomial Approximation Scheme, Terms Algorithms Keywords