Sciweavers

101 search results - page 13 / 21
» Parallel constrained coding with application to two-dimensio...
Sort
View
ICS
2009
Tsinghua U.
14 years 3 months ago
Adagio: making DVS practical for complex HPC applications
Power and energy are first-order design constraints in high performance computing. Current research using dynamic voltage scaling (DVS) relies on trading increased execution time...
Barry Rountree, David K. Lowenthal, Bronis R. de S...
CASES
2007
ACM
14 years 12 days ago
Application driven embedded system design: a face recognition case study
The key to increasing performance without a commensurate increase in power consumption in modern processors lies in increasing both parallelism and core specialization. Core speci...
Karthik Ramani, Al Davis
ICPP
2007
IEEE
14 years 2 months ago
CPU MISER: A Performance-Directed, Run-Time System for Power-Aware Clusters
Performance and power are critical design constraints in today’s high-end computing systems. Reducing power consumption without impacting system performance is a challenge for t...
Rong Ge, Xizhou Feng, Wu-chun Feng, Kirk W. Camero...
ISCAS
2005
IEEE
152views Hardware» more  ISCAS 2005»
14 years 2 months ago
Dictionary-based program compression on transport triggered architectures
— Program code size has become a critical design constraint of embedded systems. Large program codes require large memories, which increase the size and cost of the chip. Poor co...
Jari Heikkinen, Andrea G. M. Cilio, Jarmo Takala, ...
ICANNGA
2007
Springer
191views Algorithms» more  ICANNGA 2007»
14 years 2 months ago
Novel Multi-layer Non-negative Tensor Factorization with Sparsity Constraints
In this paper we present a new method of 3D non-negative tensor factorization (NTF) that is robust in the presence of noise and has many potential applications, including multi-way...
Andrzej Cichocki, Rafal Zdunek, Seungjin Choi, Rob...