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GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
14 years 3 months ago
Transition-activity aware design of reduction-stages for parallel multipliers
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Osc...
SPAA
2005
ACM
14 years 2 months ago
Randomization does not reduce the average delay in parallel packet switches
Switching cells in parallel is a common approach to build switches with very high external line rate and a large number of ports. A prime example is the parallel packet switch (in...
Hagit Attiya, David Hay
GECCO
2006
Springer
143views Optimization» more  GECCO 2006»
14 years 25 days ago
A hybridized genetic parallel programming based logic circuit synthesizer
Genetic Parallel Programming (GPP) is a novel Genetic Programming paradigm. Based on the GPP paradigm and a local search operator - FlowMap, a logic circuit synthesizing system in...
Wai Shing Lau, Kin-Hong Lee, Kwong-Sak Leung
ICS
2000
Tsinghua U.
14 years 23 days ago
Automatic loop transformations and parallelization for Java
From a software engineering perspective, the Java programming language provides an attractive platform for writing numerically intensive applications. A major drawback hampering i...
Pedro V. Artigas, Manish Gupta, Samuel P. Midkiff,...
IOPADS
1996
87views more  IOPADS 1996»
13 years 10 months ago
Structured Permuting in Place on Parallel Disk Systems
The ability to perform permutations of large data sets in place reduces the amount of necessary available disk storage. The simplest way to perform a permutation often is to read ...
Leonard F. Wisniewski