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NPC
2010
Springer
15 years 27 days ago
Exposing Tunable Parameters in Multi-threaded Numerical Code
Achieving high performance on today’s architectures requires careful orchestration of many optimization parameters. In particular, the presence of shared-caches on multicore arch...
Apan Qasem, Jichi Guo, Faizur Rahman, Qing Yi
128
Voted
ICPP
2008
IEEE
15 years 9 months ago
On the Design of Fast Pseudo-Random Number Generators for the Cell Broadband Engine and an Application to Risk Analysis
Numerical simulations in computational physics, biology, and finance, often require the use of high quality and efficient parallel random number generators. We design and optimi...
David A. Bader, Aparna Chandramowlishwaran, Virat ...
LCPC
2004
Springer
15 years 7 months ago
A Geometric Approach for Partitioning N-Dimensional Non-rectangular Iteration Spaces
Abstract. Parallel loops account for the greatest percentage of program parallelism. The degree to which parallelism can be exploited and the amount of overhead involved during par...
Arun Kejariwal, Paolo D'Alberto, Alexandru Nicolau...
HPCA
1999
IEEE
15 years 6 months ago
Improving CC-NUMA Performance Using Instruction-Based Prediction
We propose Instruction-based Prediction as a means to optimize directory-based cache coherent NUMA shared-memory. Instruction-based prediction is based on observing the behavior o...
Stefanos Kaxiras, James R. Goodman
ISCAS
2006
IEEE
82views Hardware» more  ISCAS 2006»
15 years 8 months ago
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing
– This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that crosscapacitances are ...
Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny