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ICEC
1994
147views more  ICEC 1994»
13 years 10 months ago
VLSI Circuit Synthesis Using a Parallel Genetic Algorithm
A parallel implementation of a genetic algorithm used to evolve simple analog VLSI circuits is described. The parallel computer system consisted of twenty distributed SPARC workst...
Mike Davis, Luoping Liu, John G. Elias
DAC
2002
ACM
14 years 10 months ago
An integer linear programming based approach for parallelizing applications in On-chip multiprocessors
With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneous...
Ismail Kadayif, Mahmut T. Kandemir, Ugur Sezer
GECCO
2008
Springer
131views Optimization» more  GECCO 2008»
13 years 10 months ago
Testing parallelization paradigms for MOEAs
In this paper, we report on our investigation of factors affecting the performance of various parallelization paradigms for multiobjective evolutionary algorithms. Different paral...
Sadeesha Gamhewa, Philip Hingston
IPPS
2006
IEEE
14 years 3 months ago
Cache-oblivious simulation of parallel programs
This paper explores the relation between the structured parallelism exposed by the Decomposable BSP (DBSP) model through submachine locality and locality of reference in multi-lev...
Andrea Pietracaprina, Geppino Pucci, Francesco Sil...
FCCM
2005
IEEE
124views VLSI» more  FCCM 2005»
14 years 2 months ago
Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA
The CLA-EC is a model obtained by combining the concepts of cellular learning automata and evolutionary algorithms. The parallel structure of the CLA-EC makes it suitable for hard...
Arash Hariri, Reza Rastegar, Morteza Saheb Zamani,...