226 search results - page 34 / 46 » Parallel mixing |
IEEEPACT
2007
IEEE
14 years 2 months ago
2007
IEEE
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
ICPP
2008
IEEE
14 years 2 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
CORR
2010
Springer
13 years 7 months ago
2010
Springer
A Gaussian interference channel (IC) with a relay is considered. The relay is assumed to operate over an orthogonal band with respect to the underlying IC, and the overall system i...
ICS
2009
Tsinghua U.
13 years 5 months ago
2009
Tsinghua U.
In the search for high performance, most transactional memory (TM) systems execute atomic blocks concurrently and must thus be prepared for data conflicts. The TM system must then...
CP
2005
Springer
14 years 1 months ago
2005
Springer
We combine mixed integer linear programming (MILP) and constraint programming (CP) to minimize tardiness in planning and scheduling. Tasks are allocated to facilities using MILP an...