360 search results - page 23 / 72 » Parallel processing flow models on desktop hardware |
APGV
2006
ACM
14 years 2 months ago
2006
ACM
This paper describes a new technique to visualize 2D flow fields with a sparse collection of dots. A cognitive model proposed by Kent Stevens describes how spatially local con...
SBACPAD
2007
IEEE
14 years 2 months ago
2007
IEEE
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
OOPSLA
2009
Springer
14 years 3 months ago
2009
Springer
Software has spent the bounty of Moore’s law by solving harder problems and exploiting abstractions, such as highlevel languages, virtual machine technology, binary rewritdynami...
ICFP
2009
ACM
14 years 9 months ago
2009
ACM
Concurrent ML (CML) is a high-level message-passing language that supports the construction of first-class synchronous abstractions called events. This mechanism has proven quite ...
ARCS
2008
Springer
13 years 10 months ago
2008
Springer
Due to increasing complexity of modern real-time image processing applications, classical hardware development at register transfer level becomes more and more the bottleneck of te...