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» Parallel processing flow models on desktop hardware
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2005
Tsinghua U.
14 years 2 months ago
Improved automatic testcase synthesis for performance model validation
Performance simulation tools must be validated during the design process as functional models and early hardware are developed, so that designers can be sure of the performance of...
Robert H. Bell Jr., Lizy Kurian John
ASPLOS
2008
ACM
13 years 10 months ago
Dispersing proprietary applications as benchmarks through code mutation
Industry vendors hesitate to disseminate proprietary applications to academia and third party vendors. By consequence, the benchmarking process is typically driven by standardized...
Luk Van Ertvelde, Lieven Eeckhout
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
14 years 1 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
CCGRID
2008
IEEE
13 years 10 months ago
Using Probabilistic Characterization to Reduce Runtime Faults in HPC Systems
Abstract--The current trend in high performance computing is to aggregate ever larger numbers of processing and interconnection elements in order to achieve desired levels of compu...
Jim M. Brandt, Bert J. Debusschere, Ann C. Gentile...
PODC
2012
ACM
11 years 11 months ago
On the (limited) power of non-equivocation
In recent years, there have been a few proposals to add a small amount of trusted hardware at each replica in a Byzantine fault tolerant system to cut back replication factors. Th...
Allen Clement, Flavio Junqueira, Aniket Kate, Rodr...