Sciweavers

360 search results - page 62 / 72
» Parallel processing flow models on desktop hardware
Sort
View
PPOPP
2005
ACM
14 years 2 months ago
Energy conservation in heterogeneous server clusters
The previous research on cluster-based servers has focused on homogeneous systems. However, real-life clusters are almost invariably heterogeneous in terms of the performance, cap...
Taliver Heath, Bruno Diniz, Enrique V. Carrera, Wa...
IPPS
2003
IEEE
14 years 1 months ago
Targeting Tiled Architectures in Design Exploration
Tiled architectures can provide a model for early estimation of global interconnect costs. A design exploration tool for reconfigurable architectures is currently under developmen...
Lilian Bossuet, Wayne Burleson, Guy Gogniat, Vikas...
EUROPAR
2011
Springer
12 years 8 months ago
A Fully Empirical Autotuned Dense QR Factorization for Multicore Architectures
: Tuning numerical libraries has become more difficult over time, as systems get more sophisticated. In particular, modern multicore machines make the behaviour of algorithms hard ...
Emmanuel Agullo, Jack Dongarra, Rajib Nath, Stanim...
IEEEPACT
2007
IEEE
14 years 2 months ago
Verification-Aware Microprocessor Design
The process of verifying a new microprocessor is a major problem for the computer industry. Currently, architects design processors to be fast, power-efficient, and reliable. Howe...
Anita Lungu, Daniel J. Sorin
DATE
2005
IEEE
135views Hardware» more  DATE 2005»
14 years 2 months ago
Compositional Memory Systems for Multimedia Communicating Tasks
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...