7 search results - page 2 / 2 » Parallel saturating multioperand adders |
GLVLSI
1999
IEEE
14 years 3 hour ago
1999
IEEE
This paper describes the designs of a saturating adder, multiplier, single MAC unit, and dual MAC unit with one cycle latencies. The dual MAC unit can perform two saturating MAC o...
ASAP
2002
IEEE
14 years 20 days ago
2002
IEEE
This paper introduces PAPA: Packed Arithmetic on a Prefix Adder, a new approach to parallel prefix adder design that supports a wide variety of packed arithmetic computations, inc...