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» Parallel signal processing with S-Net
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FPL
2010
Springer
170views Hardware» more  FPL 2010»
13 years 5 months ago
IP Based Configurable SIMD Massively Parallel SoC
Significant advances in the field of configurable computing have enabled parallel processing within a single FieldProgrammable Gate Array (FPGA) chip. This paper presents the imple...
Mouna Baklouti, Mohamed Abid, Philippe Marquet, Je...
DAC
2007
ACM
13 years 11 months ago
Programming Living Cells to Function as Massively Parallel Computers
We have reprogrammed the genomes of living cells to construct massively parallel biological computers capable of processing two-dimensional images at a theoretical resolution of g...
Jeffrey J. Tabor
ESANN
2008
13 years 8 months ago
Parallel asynchronous neighborhood mechanism for WTM Kohonen network implemented in CMOS technology
In this paper we present an original neighborhood mechanism for WTM self-organizing Kohonen map implemented in CMOS 0.18 m process. Proposed mechanism is an asynchronous circuit an...
Marta Kolasa, Rafal Dlugosz
FPL
2008
Springer
163views Hardware» more  FPL 2008»
13 years 9 months ago
Towards an "early neural circuit simulator": A FPGA implementation of processing in the rat whisker system
We have constructed a FPGA-based "early neural circuit simulator" to model the first two stages of stimulus encoding and processing in the rat whisker system. Rats use t...
Brian Leung, Yan Pan, Chris Schroeder, Seda Ogrenc...
IPPS
1999
IEEE
13 years 11 months ago
Process Tracking for Parallel Job Control
Job management subsystems in parallel environments have to address two important issues: (i) how to associate processes present in the system to the tasks of parallel jobs, and (ii...
Hubertus Franke, José E. Moreira, Pratap Pa...