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VLSID
1996
IEEE
119views VLSI» more  VLSID 1996»
14 years 3 months ago
Parallel simulated annealing strategies for VLSI cell placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process, and as a result several research efforts have been un...
John A. Chandy, Prithviraj Banerjee
IPPS
2006
IEEE
14 years 4 months ago
Evaluating parallel simulated evolution strategies for VLSI cell placement
Simulated Evolution (SimE) is an evolutionary metaheuristic that has produced results comparable to well established stochastic heuristics such as SA, TS and GA, with shorter runti...
Sadiq M. Sait, Mustafa I. Ali, Ali Mustafa Zaidi
ICCD
1997
IEEE
123views Hardware» more  ICCD 1997»
14 years 3 months ago
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
John A. Chandy, Prithviraj Banerjee
ISCAS
2005
IEEE
133views Hardware» more  ISCAS 2005»
14 years 4 months ago
Multiobjective VLSI cell placement using distributed simulated evolution algorithm
— Simulated Evolution (SimE) is a sound stochastic approximation algorithm based on the principles of adaptation. If properly engineered it is possible for SimE to reach nearopti...
Sadiq M. Sait, Ali Mustafa Zaidi, Mustafa I. Ali
JUCS
2008
139views more  JUCS 2008»
13 years 10 months ago
Parallel Strategies for Stochastic Evolution
: This paper discusses the parallelization of Stochastic Evolution (StocE) metaheuristic, for a distributed parallel environment. VLSI cell placement is used as an optimization pro...
Sadiq M. Sait, Khawar S. Khan, Mustafa Imran Ali